When Gordon Moore first spotted the trend that carries his name, only about 50 transistors could economically fit on an integrated circuit. Since the Intel 4004 microprocessor arrived in 1971, the linear size of a MOS transistor has shrunk by a factor of roughly 1,000, and the number of transistors on one chip has grown about 15-million-fold.
That run is what Moore’s Law describes, and for more than 55 years it has been tracked through “technology nodes,” waypoints that arrive roughly every two years. The node number is the thing everyone quotes. A 2020 IEEE Spectrum commentary argued it has been meaningless for about two decades.
Where the numbers came from
Originally the node tracked two real measurements: gate length, the space between a transistor’s source and drain, and metal half-pitch, half the distance from one metal interconnect to the next. For a long time they were about the same number. Chipmakers cut both by about 30 percent each generation, which halves the area and so doubles the transistor count.
In the mid-1990s the two came apart. Chipmakers shrank gate length faster than anything else to squeeze out speed and efficiency. Transistors from the 130-nm node, for example, actually had 70-nm gates. The industry kept using the old naming anyway.
By 2011, when Intel moved to FinFETs at the 22-nm node, the devices had 26-nm gates, a 40-nm half-pitch and fins 8 nm wide. Paolo Gargini, an IEEE Life Fellow and Intel veteran, said the node number “had by then absolutely no meaning, because it had nothing to do with any dimension that you can find on the die.”
Think of it like a shoe size that stopped matching anyone’s foot but stayed printed on every box.
A three-number replacement
Gargini, who chairs the IEEE International Roadmap for Devices and Systems, proposed in April 2020 that the industry adopt a metric with three values: contacted gate pitch (G), metal pitch (M) and the number of device tiers (T). “These three parameters are all you need to know to assess transistor density,” he said.
The roadmap’s upcoming 5-nm chips would read G48M36T1: a 48-nm contacted gate pitch, a 36-nm metal pitch and a single tier. Brian Cline, a principal research engineer at Arm, called the first two values the “least common denominator” for building logic in a new process, because multiplied together they estimate the smallest possible transistor area.
The commentary pointed out why the third number matters. Extreme ultraviolet lithography works with 13.5-nanometer light, and Gargini said that “around 2029, we reach the limit of what we can do with lithography.” After that, he said, “the way forward is to stack.”
Stacking two layers of transistors might nearly double density. For silicon that is still lab work, because the heat needed to build one layer can damage another. Imec, France’s CEA-Leti and Intel are all working on it. Carbon-nanotube chips, which can be built at lower temperatures, could get to multiple tiers sooner; MIT professor Max Shulaker and colleagues have been developing them.
The idea of a new metric was already circulating. In June 2019, a group of prominent academics met at the University of California, Berkeley, to draft one of their own, including Chenming Hu, Tsu-Jae King Liu and Jeffrey Bokor, the three Berkeley engineers credited with the FinFET.
