Home » Intel Squeezes 1.58-Bit LLM to 1.485 Bits, No Weight Changes

Intel Squeezes 1.58-Bit LLM to 1.485 Bits, No Weight Changes

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Intel Squeezes 1.58-Bit LLM to 1.485 Bits, No Weight Changes

SANTA CLARA, September 19 — Intel researchers have demonstrated a way to squeeze a large language model that was already quantized to 1.58 bits per weight down to an average of 1.485 bits per weight, without altering a single one of the model’s original weight values. The technique is laid out in a paper titled “Optimizing 1.58-bit LLMs: A Comprehensive Study,” published on arXiv on February 28, 2025.

It targets models like BitNet b1.58, the ternary-weight architecture Microsoft Research introduced in its own paper, “The Era of 1-bit LLMs: All Large Language Models are in 1.58 Bits,” on February 27, 2024. BitNet b1.58 runs on ternary weights — values of -1, 0 or 1 — that theoretically require log2(3) ≈ 1.585 bits per weight to store.

Intel’s approach gets the average down to 1.485 bits by combining two techniques: a custom encoding scheme that maps the ternary values to binary codes of varying lengths, and a grouping strategy that stores the most frequent weight values with fewer bits.

Lossless, and that matters

The method is lossless with respect to the original weights. No weight is modified, and the model’s outputs remain identical to the 1.58-bit baseline. The savings come from exploiting the statistical distribution of weights in trained models, which tend to hold many zeros and fewer -1s and 1s.

Assigning shorter codes to zeros and longer codes to non-zero values pulls the average bits per weight below the theoretical minimum for fixed-length encoding. The paper reports experiments on models ranging from 700 million to 7 billion parameters, showing the technique reduces memory usage by approximately 6% compared to standard 1.58-bit storage, with no degradation in perplexity or accuracy on benchmarks such as WikiText-2 and LAMBADA.

Intel’s work builds on the growing interest in low-bit quantization for efficient inference, particularly for edge devices and data centers where memory bandwidth is a bottleneck. The researchers note the method is compatible with existing 1.58-bit training pipelines and can be applied as a post-processing step. The paper’s authors include Intel Labs researchers and collaborators from academic institutions.

The development was first reported by technology news outlets in early March 2025.

What to watch

This advance could make ternary LLMs even more attractive for deployment on resource-constrained hardware, since it further shrinks the memory required to store model weights. The practical impact, though, depends on whether the encoding and decoding overhead can be kept low enough not to offset the memory savings during inference. Intel has not announced a product based on this research, but the company has been actively promoting its AI hardware and software stack, including Gaudi accelerators and OpenVINO toolkit.

The paper is available on arXiv and has been discussed in AI research communities. The key takeaway is that Intel has found a way to store ternary weights more efficiently without changing them, pushing the effective bit-width below the theoretical limit for fixed-length encoding of three values.

It is an incremental but notable optimization for the field of low-bit LLMs — and the next question is whether the decode overhead stays small enough to make the savings count in production.

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