On June 27, Marvell updated its Structera line of CXL controllers, and the headline is a deceptively simple idea: instead of buying more memory, squeeze the memory you already have. The Structera X memory expansion controller attacks one of the least glamorous bottlenecks of the AI era — the capacity and bandwidth wall that servers hit when models and in-memory databases grow faster than DRAM budgets. The tool of choice is hardware inline compression, delivered by a dedicated block on the chip.
How It Works, And What The Numbers Say
Early findings from the company suggest the approach is more than a party trick. The controller’s CDB module — short for Compression-Decompression Block — runs a customized version of the lossless LZ4 algorithm, packing data down as it is written to DRAM and unpacking it on readout. Because the work happens in hardware, host CPUs and operating systems see nothing of it: applications need no code changes. In mixed real-world tests, Marvell reports that database-type data compresses at 3.64x, XML at 2.75x and source code at roughly 2.00x. A page of all zeros, admittedly the friendliest case, can compress at up to 64:1. Operators can tune the effort, with compression levels configurable between 0 and 3.
The encouraging part for data center operators is what effective compression does to capacity: more usable memory from the same physical DIMMs, easing pressure exactly where AI workloads feel it most. The cautious part, as with any vendor benchmark, is that real ratios depend on the data — text-heavy and structured loads reward compression far better than already-dense media or encrypted streams do.
Two Models, One Architecture
The series splits along memory generations. The Structera X 2504 supports DDR5 at 6400 MT/s, up to 2 DIMMs per channel and capacities beyond 6TB, while the Structera X 2404 serves DDR4 at 3200/1600 MT/s, takes 3 DIMMs per channel and tops 4TB. Both share the same skeleton: four ARM Cortex-M7 cores, CXL 2.0 and PCIe 5.0 connectivity, peak memory bandwidth of 200 GB/s, and inline XTS-AES 256-bit encryption with Secure Boot baked in. Compatibility with mainstream Intel and AMD server platforms is part of the pitch, and the 2404 is built on a 5nm process.
The DDR4 variant carries a sustainability angle worth noting. Released in December 2025, it is aimed at putting retired DDR4 modules back to work in servers — extending the life of hardware that would otherwise be scrapped, cutting data center costs in the process.
A Short Track Record, A Growing Standard
Structera is not a newcomer. The line won an Innovative Sustainable Technology Award at the Flash Memory Summit in August 2024, and in April 2025 the original Structera X claimed an industry first as the earliest CXL memory expander with LZ4 compression, an advance Marvell said could double accessible memory capacity. The June 2026 update extends the CDB compression block across both Structera X and its sibling Structera A, and the family — which also includes Structera S — was early in submitting its hardware inline memory compression spec to the Open Compute Project.
The diagnosis is credible: memory is often the scarcest resource in modern AI infrastructure, and doubling effective capacity without doubling spend is a real fix. Buyers should weigh their own data mix against the published ratios. But as a direction for the industry — efficiency engineered into the controller rather than bolted on afterward — the Structera refresh points somewhere sensible.
