Here’s what it means when people say AI data centers have a memory problem: the chips are fine, the RAM is not. Server-grade DDR5 RDIMM spot prices have surged 300% to 400% since mid-2025, landing at $27 to $37 per gigabyte, according to pricing tracked by Trendforce and the Sourceability newsletter. Add it up and a standard 12TB memory pool now carries a raw hardware cost of nearly half a million dollars. Recommendation models, LLM inference, in-memory databases, vector search — the fashionable workloads are all thirsty, and the drink has become the most expensive item on the menu.
Marvell’s answer is a family of CXL devices called Structera, and the cleverest piece is almost embarrassingly simple: a dedicated hardware block, the Compression-Decompression Block, that squeezes data losslessly 2:1 using LZ4 at full line speed, with no help and no notice from the host CPU or operating system. Think of it like vacuum bags in a suitcase. You fit twice the clothes into the same case, and nobody at the airport can tell. Because the compression happens in silicon, cloud operators can effectively halve the cost per gigabyte of their memory pools without buying more physical DIMMs, modifying servers, or rewriting software.
The second trick is about distance. CXL, the industry-standard way to bolt extra memory onto servers over PCIe, has a catch: reaching that external tier adds 100 to 200 nanoseconds, and clumsy software management of memory placement can set off page-migration chaos that wrecks response times at the tail. Marvell pushes the fixes into hardware. The Structera X expander presents a vast virtual address space so those constant page moves stop being necessary. The Structera A accelerator goes further, planting 16 Arm Neoverse V2 cores of server class right on the controller, so jobs like vector search and recommendation models run next to the data instead of hauling it across the bus. After buying XConn Technologies, Marvell added sub-microsecond Structera S switches, tying expanders and accelerators into a full CXL 2.0/3.0 pooling fabric.
In plain terms, the market positioning is a full stack versus parts. Astera Labs, with its Leo CXL memory controller, plus Broadcom and Montage Technology, sell capable components; the research note behind this analysis, by Ron Westfall, argues Marvell’s breadth — compression, near-memory compute, and switching together — is what dodges the software tangles and tail-latency hits that plague single-piece rivals. Marvell also claims an industry first: verified, production-ready interoperability across the major CPU platforms, Intel and AMD, and both DDR4 and DDR5 memory tiers. Two quieter benefits matter to operators: compression in silicon frees host CPU cycles, and pools can absorb older DIMMs rather than landfilling them.
The practical upshot for anyone watching AI infrastructure costs: the battle has moved from raw compute to what the analyst note calls “the AI memory wall” — and the weapon of choice may be a compression engine nobody sees. Marvell has also hedged its bets by offering its CXL intellectual property for custom ASIC integration, so the architecture can end up inside other companies’ chips. Whether cloud providers adopt the whole stack or just the idea, the math is the selling point — when a gigabyte costs as much as a decent chair, doubling effective capacity for free is not a niche feature. It is the whole ballgame.
