Home » Nvidia Unveils Blackwell GPU Microarchitecture at GTC 2024

Nvidia Unveils Blackwell GPU Microarchitecture at GTC 2024

By

–

Nvidia Unveils Blackwell GPU Microarchitecture at GTC 2024

In October 2023, a slide in Nvidia’s investor presentation quietly replaced the words “Hopper-Next” with two product names, the B100 and B40. That was the first official sign of Blackwell. The architecture itself was announced on March 18, 2024, at the company’s GTC keynote.

The name had leaked in 2022. Blackwell succeeds Hopper in the data center and Ada Lovelace in gaming, and it honors David Blackwell, an American mathematician known for game theory, probability theory, information theory and statistics. He was the first African American scholar inducted into the National Academy of Sciences.

Why the timing mattered

Hopper had been a hit. Demand through 2023 was so heavy that H100 servers took 36 to 52 weeks to arrive, and Nvidia reportedly sold 500,000 H100s in the third quarter of 2023 alone. Its market value passed $2 trillion, behind only Microsoft and Apple. The October roadmap also signalled a shift from a two-year release cycle for data center products to a yearly one.

At GTC the focus was on the B100 and B200 accelerators, the eight-GPU HGX B200 board and the 72-GPU NVL72 rack. Jensen Huang, Nvidia’s CEO, said “we created a processor for the generative AI era.” Nvidia showed off endorsements from the heads of Google, Meta, Microsoft, OpenAI and Oracle. The keynote did not mention gaming.

Under the hood

Blackwell is built on TSMC’s custom 4NP process for data center parts and 4N for consumer parts. Because that is only a small step from the process Hopper used, the gains had to come from the design itself.

The GB100 die holds 104 billion transistors, 30% more than Hopper’s GH100 at 80 billion. It sits at the reticle limit, the biggest pattern lithography can print in one pass. Nvidia’s answer is to put two GB100 dies in one package, joined by a 10 TB/s link it calls NV-HBI. The pair behaves like one large chip with full cache coherency and totals 208 billion transistors.

Huang told CNBC that Nvidia spent about $10 billion on research and development for that interconnect. Jim Keller, a veteran chip engineer, disputed the figure and argued that Ultra Ethernet could have done the job for $1 billion.

The fifth-generation Tensor Cores add MXFP4 and MXFP6 formats, and Nvidia claims 20 petaflops of FP4 compute for the dual-GPU GB200 superchip, not counting its 2x claim for sparsity. Fourth-generation ray tracing cores arrive too, along with an AI Management Processor, a RISC-V scheduler on the GPU that takes work off the CPU.

On the consumer side, the largest die, GB202, measures 750mm2 and has 24,576 CUDA cores, 28.5% more than Ada Lovelace’s largest.

After launch

In October 2024 it emerged that a design flaw had cut yields. Huang called it “functional” and said it was fixed with TSMC. By November, Morgan Stanley reported that all of Blackwell’s 2025 production was already sold out.

Sources

Sources

Related stories

Get breaking stories first on our Telegram channel.

More stories by

Most read

Electronics & Computing

Cybersecurity

Gadgets & Reviews

Business