A chip layout can work perfectly in simulation and still fail the check that decides whether a foundry will make it. Siemens and TSMC say they have an AI agent that finds those failures and fixes them.
The agent targets design rule violations, the errors that stop a layout being manufactured as planned. It links Siemens’ Calibre verification software with its Aprisa and Solido design tools. Rather than leaving engineers to diagnose each violation and make every correction by hand, the agent is meant to spot the problem, study its context, suggest or carry out a fix, then check the result. Both companies say that should cut manual work and shorten the road to tapeout, the moment a finished design goes off for manufacturing.
Why the fixes are fiddly
Modern chips hold enormous numbers of features, and every new manufacturing process comes with detailed rules on how they can be placed and connected. Repairing one violation can create another, or nudge power use, speed or chip area. Verification is a loop that runs through development, not a box ticked at the end.
That is also why the task suits an AI agent. A violation has a specific context, and established software can confirm whether the fix worked. Still, a passing check does not prove the change was the best one for the whole chip. Engineers will keep judging trade-offs, especially where timing, power or reliability are involved.
Bigger ambitions
The companies describe a wider goal for Siemens’ Fuse EDA AI system: agents that work through long, multistep jobs across several tools and validate their own output. The collaboration also reaches custom chip design and the placement and routing of digital circuits.
It goes beyond AI, too. Siemens says its tools support several TSMC process technologies and parts of the 3DFabric packaging platform. In 3D designs, engineers may stack chips or join separate pieces of silicon, often called chiplets, in a single package, which raises problems with chip-to-chip connections, signal quality and heat. Siemens reports expanded verification support for stacked designs, thermal analysis work and continuing development of chip and package flows. Some capabilities are certified for particular TSMC technologies; others are still in development or certification. Siemens and TSMC are also extending training resources to TSMC design partners.
The announcement describes capabilities and expected benefits, but offers no customer results showing how much time or money the agent saves. That is the number that will matter: fewer hours spent on violations, faster design cycles, and chips that hit their targets once built.
