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Marvell’s New Chips Target Memory Crunch with Data Compression

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Marvells New Chips Target Memory Crunch with Data Compression

The memory industry has a math problem. AI models swallow RAM at rates that make hardware engineers wince, and the supply chain for memory chips has been tight for years. Marvell Technology, a company based in Santa Clara, believes it has found a partial solution — and it does not involve building more factories or digging more silicon.

On June 27, Marvell announced its Structera CXL controllers, two chips that can compress data stored in memory by up to 3.64 times. The controllers are named Structera X and Structera A.

Both belong to Marvell’s CXL family, a standard for connecting processors and memory over a high-speed link. What sets them apart from competing CXL controllers is a dedicated block of hardware called the Compression-Decompression Block, or CDB. This block is the core of the product.

It is a purpose-built silicon solution that operates at full bandwidth. When data is written to DRAM, the CDB compresses it.

When that data is read back, the CDB decompresses it. The process happens in real time, without involving the host CPU. That is a key distinction.

Most software-based compression slows a system down because it demands processor cycles. Marvell’s hardware block operates independently, leaving the CPU free for other work. The company says its compression block adheres to specifications submitted to the Open Compute Project.

According to Marvell, this makes the Structera controllers the only CXL memory controllers offering inline compression as an in-production feature. The practical effect is straightforward.

A server with 256 gigabytes of DRAM could, under the right conditions, behave as if it had over 900 gigabytes. The compression ratio of 3.64x is the ceiling, not the floor. Real-world results will depend on the data being stored.

Compressible data — logs, text, model weights with redundancy — will compress well. Random data will not compress at all.

But for AI workloads, which often involve large, repetitive matrices, the gains can be substantial. This matters because the broader tech industry faces widespread shortages of memory and storage solutions. AI workloads consume memory at an unprecedented rate.

Demand for high-capacity DRAM has outpaced supply. Prices have climbed. Data center operators are looking for ways to stretch every gigabyte.

Marvell’s approach does not increase the physical amount of memory in a system. It makes the existing memory hold more.

Think of it as packing a suitcase. Without compression, you fill the space and you are done. With compression, you fit more into the same volume.

The suitcase does not get bigger. The contents just get denser.

Marvell is not the only company working on memory compression. But most CXL controllers on the market today provide no compression at all. They move data.

They do not shrink it. The Structera controllers add a layer of intelligence to the memory path that competing hardware lacks. The announcement lands at a moment when the memory industry is under heavy strain.

DRAM makers are running at capacity. NAND flash supply is tight.

AI training clusters require enormous pools of high-bandwidth memory. Inference workloads, which run trained models, also demand large memory footprints. Every byte saved by compression is a byte that does not need to be manufactured, shipped, or powered.

Marvell’s solution is hardware, not software. That matters for adoption.

Software compression requires changes to operating systems, hypervisors, or applications. Hardware compression at the memory controller level is transparent. The operating system sees the same memory capacity.

The application sees the same memory capacity. The compression happens beneath both, invisible to the user. The company has not disclosed pricing or availability dates for the Structera X and Structera A.

It has not named any customers. But the logic of the product is clear.

Memory is scarce. Compression is cheap. And the CDB block, designed to the Open Compute Project specification, gives data center operators a path to denser memory without waiting for denser chips.

{“@context”: “https://schema.org”, “@type”: “NewsArticle”, “headline”: “Marvell’s New Chips Target Memory Crunch with Data Compression”, “description”: “The memory industry has a math problem. AI models swallow RAM at rates that make hardware engineers wince, and the supply chain for memory chips…”, “datePublished”: “2026-06-27T13:42:00+00:00T09:30:00+00:00”, “author”: {“@type”: “Person”, “name”: “Muhammad Asim”}, “publisher”: {“@type”: “Organization”, “name”: “InfoPulse Today”, “url”: “https://newsfeed.infopulsetoday.com/”}}

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